1. Technical Field
This invention generally relates to semiconductor processing and more specifically relates to defect monitoring in semiconductor processing.
2. Background Art
An ongoing concern in semiconductor technology is the maximization of fabrication yield. One factor that leads to a reduction in fabrication yield is the presence of process-induced defects in the semiconductor device. Random defects are typically caused by foreign material (FM), particularly in the form of particles. The result of these defects are frequently circuit failure caused by unwanted shorts in conductive lines, between adjacent conductive lines, or between overlying conductive lines.
An analysis of the process-induced defects can be very useful in identifying and eliminating yield detractors. However, because of the complexity of modern Very Large Scale Integrated (VLSI) circuits, testing the actual semiconductor devices is very time consuming and costly. Additionally, the information gained from testing the actual devices is limited, as it is often impossible to determine the extent and frequency of the processing defects.
As a result of the above problems, it is preferable to fabricate special semiconductor-processing defect monitors that are dedicated to the analysis of processing defects. These defect monitors are built with structures comparable to those in the VLSI devices, but in such a way that the presence of defects in the defect monitors are more easily ascertained. These defect monitors are typically constructed at the same time but in a different location on the semiconductor substrate than the operation VLSI devices, and are discarded once the useful defect information is extracted from them.
These defect monitors can be used either by periodically fabricating a wafer with the defect monitor in the production line, or by including the defect monitor in otherwise unused portions of the semiconductor wafer. The latter approach has the advantage of having the defect monitor fabricated in the exact processing environment as the actual VLSI devices. Thus, the defects in the defect monitors more accurately reflect the defects that exist in the actual VLSI device.
For the same reason, it is desirable that the defect monitors use the same structure types and geometries found in the actual device, and are thus preferably manufactured using the same technologies as the actual device.
In the prior art, defect monitors that detect shorts between conductor levels (such as local conductor to polysilicon or first metal layer to local conductor in current DRAM and LOGIC technologies) are either limited to detecting the presence or absence of shorting defects or requiring sophisticated array circuits and time consuming analysis to locate defects and determine their size and distribution.
Therefore what is needed is a defect monitor that can more easily locate defect size and distribution, specifically, the size and distribution of interlevel defects.